`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    22:49:58 08/11/2013 
// Design Name: 
// Module Name:    ClockDivider 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module ClockDivider
	#(parameter numOfClocks = 1)
	(input clkInput,
    output reg [numOfClocks-1:0]halfs 
    );
	 
	 initial halfs <= 1; // the flop introduces lag of 1 cycle. starting at 1 fixes that.
	 always @(posedge clkInput) halfs <= halfs + 1'b1;

endmodule
